This disclosure relates generally to circuitry for recovering data information from a serial data signal received by the circuitry, and more particularly the area of signal adaptation, including dLev adaptation and variable gain amplifier adaptation, for a partial response summation node.
Communication of data between components of a system by means of so-called high-speed serial data signals is of increasing interest and importance to electronic system designers and users. Illustrative use of high-speed serial data signals is for conveying data from one programmable logic integrated circuit (“IC”) in a system to another programmable logic IC in the system or between components of the same such IC.
A problem that is common to many uses of high-speed serial data signals is that they are generally subject to loss of clarity or fidelity as they propagate through whatever medium is used to transmit them. Such loss of fidelity (which can also be characterized using any of many other terms such as signal degradation, attenuation, loss, noise, inter-symbol-interference (“ISI”), etc.) tends to become more of a problem as the data rate (serial bit rate) of the signal increases. The higher the data rate of a serial data signal, the more transmission degradation it is generally subject to. Degradation of a high-speed serial data signal (e.g., as described above from a programmable logic IC transmitting that signal through a transmission medium to another programmable logic IC receiving the signal) increases the difficulty that the receiving (receiver, “RX”) IC has in correctly interpreting the data information in the received signal.
To help compensate for the signal degradation that can cause or contribute to RX data interpretation errors, an RX IC may be equipped with any one or more of so-called equalization and/or adaptation circuits for processing of a received high-speed serial data signal (e.g., prior to any attempt to recover data information from that signal in more downstream circuitry). In particular, signal degradation due to ISI may require the use of specialized adaptive recovery circuits. For example, Forward Equalization (e.g., R-C/FFE) circuits and Decision Feedback Equalizer (DFE) circuits may be used at the receiver end. Of these, DFE is generally regarded as the most powerful at removing Post-Cursor ISI. A DFE may have multiple “taps,” each of which may include a circuit for multiplying a respective earlier (previously received) data bit value (e.g., the kth data bit value prior to the current bit) by a respective tap coefficient Ck and additively combining all of the resulting products with the incoming signal for the current bit. The DFE is able to find optimal sets of DFE tap coefficient values so that an acceptably low bit error rate is achieved by the RX IC in recovering the data information from the received serial data signal.
A DFE may also include a summation node that uses the coefficient value to filter the received signal. The summation node may be a partial summation node, which makes use of a data slicing level (“dLev”) to “slice” an error value representative of the errors caused in a received serial data signal by ISI. (The value dLev may be used in the determination of whether a symbol in a received signal is a logic one or a logic zero.) In general, dLev has been a static setting (e.g., set via configuration bits) in a programmable logic IC. This static setting may limit the quality of the results of signal conditioning adaptive recovery circuits and may also make performance prone to environmental variations such as variations in temperature, voltage, or noise. Moreover, although dLev adaptation may be used with full response/full rate DFE structures, the timing of these type of DFE structures may not be closed for high speeds such as 28 Gbps for a 20 nanometer process node. Moreover, the use of half rate DFE structures may require an excessive number of high speed multipliers and sense amplifiers (that may cause excessive loading on the summation node, increase intrinsic kickback noise generated on the summation node, and increase cost and area required for the RX) and high speed multiplexers.
Furthermore, the summation node may need a defined signal amplitude level for the received signal. The dynamic range of the received signal may be undefined, and there may be transmitter output voltage variations, channel loss characteristics that cause amplitude variation, and due to the frequency response of any RX buffers used when the incoming signal is received, the amplitude of the received signal may be uncertain.
As used herein, a bit is a binary digit, typically having a value of either 1 or 0. As used herein, the singular term “serial data signal” will generally be used as a generic term for both single-ended and differential serial data signals (even though a differential serial data signal actually includes two complementary signal constituents).